Pixel Array With Global Shutter

ABSTRACT

A pixel comprises a pinned photodiode for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the pinned photodiode and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage.

This application is a divisional of U.S. patent application Ser. No.13/344,095, filed Jan. 5, 2012, now allowed, which is a divisional ofU.S. patent application Ser. No. 12/408,975, filed Mar. 23, 2009, nowU.S. Pat. No. 8,569,671.

FIELD OF THE INVENTION

This invention relates to a pixel, and to an array of pixels, for use insemiconductor image sensors.

BACKGROUND TO THE INVENTION

CMOS image sensors are used in a wide range of applications. In manyapplications, the sensor is operated with a so-called rolling shuttermode. If the exposure period needs to be reduced, the timing of thesensor is adapted so that only a sub-set of the total set of rows in thesensor array are integrating light during the image readout time. Thissub-set of rows can be considered as a window which rolls over the focalplane array, hence the name ‘rolling shutter’.

Some applications, such as machine vision and motion analysis, demand aglobal shutter (also called a snapshot shutter) which allows the captureof all of the pixels of the sensor during the same time period. Thereare two main types of global shutters: a triggered global shutter and apipelined global shutter. In a triggered global shutter the image mustbe read out before the next image can be captured. In a pipelined globalshutter a new image can be captured during the readout of the image datafrom the previous image. Triggered global shutters are typically used inmachine vision where an object needs to be inspected. Pipelined globalshutters are typically used in motion analysis and high frame ratecameras. In a continuous recording mode, a pixel with a pipelinedshutter is sensitive at all times.

Image sensors can be implemented using Charge Coupled Device (CCD)technology or Complementary Metal Oxide Semiconductor (CMOS) technology.An interline-transfer CCD device inherently allows pipelined globalshutter operation. However, it is more difficult to implement a globalshutter in CMOS image sensors. There have been several proposals forproviding a global shutter in a CMOS image sensor. U.S. Pat. No.7,224,389 shows a pipelined synchronous shutter pixel. The pixelcomprises a photodiode, a reset transistor, a first buffer amplifier, asample capacitor and a second buffer amplifier. The next image can beacquired during readout of an image, thus allowing pipelined shutteroperation. The pixel does not allow cancelling non-uniformities causedby threshold voltage variations in the buffer amplifier or resettransistors in pipelined shutter operation. There is no possibility toobtain a reference level of the pixel during readout of the image,without destroying the signal on the photodiode, which will be capturingthe next image in pipeline shutter operation.

The paper “A 600×600 pixel, 500 fps CMOS Image Sensor with a 4.4 μmPinned Photodiode 5-Transistor Global Shutter Pixel”, I. Takayanagi, etal, proc. International Workshop on Image Sensors, Maine, June 2007, p.287 describes a 5-transistor pixel which can perform a pipelined shutteroperation and fixed pattern noise correction. U.S. Pat. No. 6,847,070shows a 5-transistor pixel with the same topology. The pixel is shown inFIG. 1 and comprises a pinned photodiode, a transfer gate, a floatingdiffusion, a reset transistor, a source follower, a selection transistorand a separate anti-blooming transistor connected to the photodiode. Thefloating diffusion is used for storage of the signal during exposure ofthe next signal. A reference level can be read out by resetting thefloating diffusion after the readout. The pixel thus allows fixedpattern noise correction and pipelined shutter operation. However,storing charges at the floating diffusion has several drawbacks. Thefloating diffusion is light sensitive, which means that the signalstored at the floating diffusion will be influenced by light collectedduring the storage time. Since the time that the signal is stored at thefloating diffusion is larger at the last rows of the image than at thefirst rows, this can create a (light-dependent) gradient in the image,with a brighter area near the last rows of the image. A second problemis that the storage node is a surface junction which has a considerableleakage current. This leakage current will be added to the signal storedon the storage node, and thereby increase the noise on the sample. Anadditional anti-blooming transistor in the pixel is utilized to drainaway excess charges, which might otherwise disturb the signal stored onthe floating diffusion. The anti-blooming transistor can also be used todrain the photodiode during part of the readout time, when the requiredshutter time is lower than the frame readout time.

U.S. Pat. No. 7,286,174 describes a dual storage node pixel which isintended to store the signal level of a photosite recorded in each oftwo different frames, such as a high-speed imaging application where ascene is differently lit between two frames. A signal level of thephotosite is transferred to one of the storage capacitors after eachexposure. This signal is either transferred in the charge domain, inwhich case the charge is converted to voltage on the storage capacitor,or in the voltage domain, in which case the signal is converted to avoltage on the photosite.

Fixed pattern noise in CMOS pixels is largely caused by thresholdvoltage variations of the different transistors inside the pixel. Thebuffer amplifier (source follower) and also the reset transistor in thepixel will have variations in threshold voltage. Some reasons for thethreshold voltage variations are local variations in dopantconcentration in the transistor channel, oxide thickness, and dopantconcentration of the gate. This threshold voltage variation results in avariable offset level of the pixel output signal. Usually, this offsetvariation is cancelled by measuring a reference level of the pixel whichdoes not contain a photosignal, and subtracting this reference levelfrom the measured signal level. To perform noise correction, the pixelmust support measurement of this reference level.

SUMMARY OF THE INVENTION

The present invention seeks to provide a pixel, and a pixel array, whichis capable of global shutter operation and which overcomes at least oneof the problems of existing pixels.

A first aspect of the present invention provides a pixel comprising:

a pinned photodiode for generating charges in response to incidentradiation;

a sense node;

a transfer gate, connected between the pinned photodiode and the sensenode, for controlling transfer of charges to the sense node;

a reset switch connected to the sense node for resetting the sense nodeto a predetermined voltage;

a first buffer amplifier having an input connected to the sense node;

a sample stage, connected to the output of the first buffer amplifier,which is operable to sample a value of the sense node; and,

a second buffer amplifier having an input connected to the sample stage.

An advantage of a pixel according to an embodiment of the invention isthat the pixel suffers much less from parasitic light sensitivity andleakage because a signal representative of the amount of radiationincident on the pinned photodiode during an exposure period is stored inthe sample stage, behind the first buffer amplifier, advantageously on acapacitor.

A further advantage of a pixel according to an embodiment of theinvention is that is possible to reset the sense node during anexposure, and to read the reset level of the sense node during anexposure without destroying the signal that is being acquired on thepinned photodiode. This can allow pixels to be operated with lower fixedpattern noise in either of the global shutter modes, i.e. triggeredglobal shutter mode and pipelined global shutter mode. The reduction offixed pattern noise is particularly important for high speed cameras,because it allows a much higher gain at the output of the image sensor.In triggered synchronous shutter mode, the temporal noise can be reducedas well. Fixed pattern noise is reduced by differential sampling of thepixel. First the signal level is read out. Then, the pixel reset levelis measured and read out. The final image is calculated by subtractingthe reset level from the signal level. This subtraction is typically,but not necessarily, performed on-chip in the column or outputamplifiers. This subtraction considerably reduces the fixed patternnoise created by spatial variations in offset level between pixels. Bothsamples share the same transistors for their readout, and will have thesame offset level. Any spatial variation in offset level amongst pixelsis not observed in the differential image.

A further advantage is that the pixel provides anti-blooming protectionthrough the existing transfer gate and reset transistor. In the case ofover-exposure of a pixel, excess charge can be drained away via thereset gate, which is conductive during the exposure, and via thetransfer gate, which is not conductive for high voltages on thephotodiode, but which starts to conduct when the voltage on thephotodiode falls below a certain voltage level, which is typicallylocated around −0.4V. Other pixel types require a separate secondanti-blooming transfer gate connected to the photodiode and leakage onthe anti-blooming transfer gate may disturb the signal captured on thephotodiode.

Advantageously, the sample stage comprises a sample switch connected toan output of the first buffer amplifier and a capacitor for storing asignal level sampled by the sample switch.

There are various circuit topologies, and timing strategies, for thepixel. In one embodiment a dedicated discharge switch is provided forresetting (discharging) the sample stage. In another embodiment, adedicated read switch is connected to the output of the second bufferamplifier for reading a signal from the pixel. In other embodiments, thefunctions of resetting (discharging) the sample stage and/or reading anoutput of the second buffer amplifier can be achieved using othercircuit elements of the pixel, with appropriate application of controlsignals to those circuit elements.

In some embodiments, the first buffer amplifier is connected to a firstcontrol line and the first control line is operable to discharge thesample stage at a certain point during an operating cycle of the pixel.

In one embodiment, the sample stage comprises a sample switch connectedto a first node and a capacitor connected in series with the sampleswitch and both of the input to the second buffer amplifier and theoutput of the first buffer amplifier are connected to the first node.

Another aspect of the invention provides a pixel array comprising anarray of pixels of the type described above, and in the accompanyingdescription, and control circuitry for controlling operation of thepixels in the array.

Advantageously, the control circuitry is arranged, for each pixel, to:operate the reset switch to reset the sense node; operate the transfergate of a pixel to transfer charge from the pinned photodiode to thesense node following exposure to radiation; cause the sample stage ofthe pixel to sample the signal on the sense node, which sampled signalrepresents an exposure level of the pixel.

Advantageously, an exposure level of a pixel and a reset level of apixel is sampled and read out to effect double sampling. The controlcircuitry can be arranged to read the sampled exposure level of thepixel. The control circuitry can be arranged to subsequently cause thesample stage to sample the sense node after it has been reset, whichsampled signal represents a reset level of the pixel. The controlcircuitry can be arranged to read the sampled reset level of the pixel.

Advantageously, a reset level of a pixel is sampled before an exposurelevel of a pixel to effect correlated double sampling. The controlcircuitry is arranged to cause the sample stage of a pixel to sample thereset level of the pixel. The control circuitry can be arranged tooperate the transfer gate of a pixel to transfer charge from the pinnedphotodiode to the sense node following exposure to radiation, whichtransferred charge represents an exposure level of the pixel. Thecontrol circuitry can be arranged to store the transferred charge at thesense node until after the reset level has been read from the samplestage.

Advantageously, the control circuitry is arranged to operate the resetswitch while the pinned photodiode is being exposed to radiation. Thiscan allow anti-blooming control, via the existing transfer gate, withoutthe need for dedicated anti-blooming gates connected to the pinnedphotodiode. The control circuitry can operate (i.e. close) the resetswitch at all times other than when it is required to transfer charge tothe sense node and sample a value of the sense node.

Advantageously, the control circuitry is arranged to read the sampledvalue of a pixel for a first exposure period while the pinned photodiodeof the pixel is exposed for a second exposure period and, moreadvantageously, the control circuitry is arranged to read a value storedin the sample stage of each pixel in the array for a first exposureperiod while the respective pinned photodiodes of the pixels in thearray are exposed for a second exposure period.

Advantageously, the control circuitry is arranged to cause the array ofpixels to be exposed synchronously.

Advantageously, at least one of: the first buffer amplifier and thesecond buffer amplifier are shared by a plurality of pinned photodiodes.This has an advantage of reducing the number of devices in the pixelarray and can simplify the layout.

The pinned photodiode has an advantage of maximising the amount oftransferred charge.

Advantageously, the pixel, or pixel array is fabricated in CMOStechnology.

Another aspect of the invention provides a pixel comprising:

a photo-sensitive element for generating charges in response to incidentradiation;

a sense node;

a transfer gate, connected between the photo-sensitive element and thesense node, for controlling transfer of charges to the sense node;

a reset switch connected to the sense node for resetting the sense nodeto a predetermined voltage;

a first buffer amplifier having an input connected to the sense node;

a first sample stage, connected to an output of the first bufferamplifier, which is operable to sample a reset level of the sense node;

a second sample stage connected to an output of the first bufferamplifier which is operable to sample a value of the sense node;

a second buffer amplifier having an input connected to an output of thefirst or second sample stages.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described, by way of example only,with reference to the accompanying drawings in which:

FIG. 1 shows a prior art 5-transistor pixel for use in performingpipelined global shutter operation;

FIG. 2 schematically shows a pixel in accordance with an embodiment ofthe invention;

FIG. 3 shows further detail of the physical structure of the pixel ofFIG. 2;

FIGS. 4 a-4 d show transistor schematics of a pixel in accordance withembodiments of the invention;

FIG. 5 shows an embodiment of the invention with a shared sample andstorage stage for two pixels;

FIGS. 6 and 15 show the architecture of a pixel array;

FIGS. 7 a and 7 b show timing diagrams for operation of the pixels shownin FIGS. 4 a-4 d;

FIG. 8 shows a timing diagram for operation of the pixel array;

FIG. 9 shows a pixel with two storage stages arranged in parallel;

FIG. 10 shows another form of a pixel with two storage stages arrangedin parallel and with a single, shared, output buffer amplifier;

FIGS. 11 and 12 show a pixel with two storage stages arranged incascade;

FIGS. 13 a and 13 b show timing diagrams for operation of the pixels ofFIGS. 11 and 12 respectively;

FIG. 14 shows a timing diagram for operation of a pixel array comprisingthe pixels of FIGS. 11 and 12.

FIG. 15 shows an overall architecture for a pixel image sensor inaccordance with embodiments of the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. Where the term “comprising” is used in thepresent description and claims, it does not exclude other elements orsteps. Furthermore, the terms first, second, third and the like in thedescription and in the claims, are used for distinguishing betweensimilar elements and not necessarily for describing a sequential orchronological order. It is to be understood that the terms so used areinterchangeable under appropriate circumstances and that the embodimentsof the invention described herein are capable of operation in othersequences than described or illustrated herein.

Throughout this specification, it should be noted that the term “row”and “column” can be interchanged. Also, the term “row” does not imply aparticular orientation of the array.

FIG. 2 schematically shows a first embodiment of a pixel 10. A fullimage sensor comprises an array of the pixels 10 shown in FIG. 2, withthe pixels typically being arranged in rows and columns. The pixel 10comprises a photodiode 11 (preferably a pinned photodiode) which isresponsive to electromagnetic or particle radiation, although mosttypically this will be light in the visible band. A transfer gate TGconnects the cathode of the photodiode 11 to a floating diffusioncapacitor C_(fd). The floating diffusion capacitor C_(fd) is typicallythe junction capacitance formed by the transfer gate TG and resettransistor source areas, although an additional dedicated capacitor canbe located at this node as well. In the following description, the terms“floating diffusion” and “sense node” refer to the same feature. Thetransfer gate TG is responsive to a control signal TRANSFER and, whenthe transfer gate TG is opened, it is able to transfer substantially allcharge from the pinned photodiode 11 to the floating diffusion capacitorC_(fd). A reset transistor (switch) is responsive to a control signalRESET and is operable to initialize the floating diffusion FD to a knownvoltage (vreset). A first buffer amplifier AMP1 buffers the voltage ofthe floating diffusion FD, at the input of the first buffer amplifier,to an output of the amplifier. A sample transistor is connected to theoutput of the first buffer amplifier AMP1 and is operable to sample thesignal level and to store the signal level on a sample capacitorC_(sample). The sample capacitor C_(sample) stores the sampled signal ofthe pixel. A second buffer amplifier AMP2 is connected to the samplecapacitor C_(sample) and is operable to buffer the signal level of thesample capacitor. An optional read switch connects the output of thesecond buffer amplifier AMP2 to a column output line 15, and is operableto select the pixel during a read out process. A preferred embodiment ofthe pixel uses a pinned photodiode 11. This ensures a low dark currentand fixed pattern noise correction. To acquire an image, each pixel isoperated as follows:

-   -   1. At the start of an exposure period, the pinned photodiode 11        is empty and does not contain any photocharges.    -   2. The image is acquired during the exposure period. Radiation        incident on the pinned photodiode 11 generates photocharges        which are collected inside the pinned photodiode 11.    -   3. (At least) at the end of the exposure time, the floating        diffusion FD is reset by pulsing the reset transistor M1. The FD        can be held in the reset state at all times except when        transferring charge transfer to the floating diffusion (step 4)        and sampling the signal (step 5).    -   4. Charge is transferred through the transfer gate TG by pulsing        the transfer line. The charge Q will generate a voltage swing on        the capacitor C_(fd). This swing is equal to Q/C_(fd).    -   5. The voltage signal is buffered by the first buffer amplifier        AMP 1 and stored on the sample capacitor C_(sample) by pulsing        the sample switch.    -   6. After the charge transfer, the photodiode 11 is depleted. It        does not contain any remaining charge. Optionally, an additional        reset can be generated to ensure that all charge is evacuated        from the photodiode 11. This reset is achieved by pulsing the        reset transistor M1 and the transfer gate TG together.    -   7. When the transfer gate TG opens again, the next exposure time        can start. This may happen immediately after this image capture        sequence or later (to reduce the exposure time below the image        read time).    -   8. Optionally, but also advantageously, the floating diffusion        can be reset again by setting the RESET line high. This allows        to drain away excess charge from the photodiode through the        transfer gate TG and reset transistor M1 during exposure of the        next image.        For global shutter operation, all of the above operations occur        synchronously for all pixels of the array. In other words, step        1 occurs at the same time for every pixel of the array, step 2        occurs at the same time for every pixel of the array, and so on.        After this image acquisition sequence, the readout of the frame        can start. For a pipelined global shutter the read out occurs        during the capture of the next frame by photodiode 11. To read        out the frame which has just been acquired, the signal sampled        on C_(sample) is read out through buffer amplifier AMP2 and the        read transistor. This is done sequentially, by scanning over the        array, row by row. The signal levels of the row are sampled in        the column amplifier (shown in FIG. 6). Then, the sample        capacitors C_(sample) of this row are reset by sampling the        reset level on capacitor C_(sample). When the reset transistors        are switched on for all pixels during the exposure, this reset        level can be simply sampled by closing the SAMPLE switch for the        row of pixels that are read out. In the case when the reset        switch is not closed, the RESET line should be pulsed together        with the SAMPLE line for the row that is read out. This reset        level is also read out and stored in the column amplifier. The        difference between this reset level and signal level is        calculated either by analog or digital circuits and output from        the sensor. This difference is free of offset errors in the        pixel or in the column amplifiers. The reading of the signal        level and reset level can be achieved without disturbing the        signal stored on the pinned photodiode 11.

FIG. 3 shows more details on the implementation of the pinned photodiodeand the transfer gate. The diode is constructed in an epitaxial layerwhich is lowly doped (typically 5E14/cm3). This epitaxial layer is grownon high conductive bulk material (p++, >1E19/cm3 or n++, >1E19/cm3). Thephotodiode is formed by a deep n-type implant, with a net concentrationnear 1E17/cm3. The surface is covered by a p++ layer (highly doped,1E19/cm3). The doping level of the n-implant is chosen such that thediode is depleted at a low voltage (near 1 V). When light enters thesilicon, it generates electron-hole pairs inside the epitaxial layer.The electrons are collected by the photodiode and the voltage on thediode falls. The diode is coupled to a transfer gate, which allows toread out the diode charge when a high voltage is applied to the transfergate. The transfer gate connects the photodiode with the floatingdiffusion. When the transfer gate is pulsed, the charge is transferredon this floating diffusion capacitor and a voltage swing will occur.

FIGS. 4 a-4 d show schematic diagrams for realising embodiments of thepixel of FIGS. 2 and 3 using transistors. FIG. 4 a shows a transistorschematic of an embodiment of the pixel which contains seven transistorsin total (transistors M1-M6 plus the transfer gate TG). M1 is the resettransistor; M2 is the first buffer amplifier; M3 is the sampletransistor; M4 is the second buffer amplifier; M5 is the readtransistor; and M6 is a discharge transistor. Each of the bufferamplifiers M2, M4 is a transistor configured as a source follower. Atransfer transistor TG is connected between the pinned photodiode 11 andfloating diffusion (sense node) FD. Reset transistor M1 is connectedbetween supply line vdd and the floating diffusion FD. Reset transistorM1 is responsive to a control signal RESET. Buffer amplifier transistorM2 has a gate connected to the floating diffusion FD and a drainconnected to supply line vdd. Sample transistor M3 is connected betweenthe output (source) of transistor M2 and the input (gate) of bufferamplifier M4. The gate of sample transistor M3 is responsive to acontrol signal SAMPLE. Sample capacitor C_(sample) is connected betweenthe input (gate) of buffer amplifier M4 and a fixed voltage level, suchas GND, VDD, or a separate voltage provided to the pixel. Dischargetransistor M6 is connected between the input (gate) of buffer amplifierM4 and ground and is responsive to a control signal DISCHARGE. Bufferamplifier M4 is configured as a source follower, with the drain of M4connected to supply line vdd and the source of M4 connected to thecolumn output line via read transistor M5. The gate of read transistorM5 is responsive to a control signal SELECT.

Before the buffer amplifier M2 samples the signal on the floatingdiffusion FD, the sample capacitor C_(sample) is discharged throughdischarge transistor M6. Then, after M6 is open again, transistor M3 isclosed and the signal of the floating diffusion FD will appear also atthe sample capacitor C_(sample) via source follower M2 and sampletransistor M3. In FIG. 4 a, the capacitor C_(sample) is dischargedthrough a dedicated transistor M6. This requires an extra groundconnection to the pixel. Although the sample capacitor C_(sample) isshown connected to ground, it may alternatively connected to anotherfixed voltage, e.g. VDD, or to a separate control line to increase thesignal swing. Transistor M6 can also be placed at the source of thesource follower/buffer amplifier M2. The sample capacitor C_(sample) isin this case discharged through discharge transistor M6 and closedtransistor M3. Note that the gate of M6 can be switched or DC. In thelatter case, M6 acts as current source load for the source follower.

FIG. 4 b shows a schematic for an alternative embodiment of the pixel.In this embodiment, discharge transistor M6 shown in FIG. 4 a is notrequired. Instead, the discharge of capacitor C_(sample) is performedvia the transistor M2. The drain of buffer amplifier M2 is connected tothe control line DISCHARGE rather than the supply line vdd as in FIG. 4a. To discharge C_(sample) the reset transistor M1 is switched on, sothat the floating diffusion FD appears at a high voltage (resettransistor M1 is typically already switched on during most of theexposure time). This will turn on M2. M3 is also switched on. The drainof M2 is pulsed low, by an appropriate signal on the DISCHARGE controlline, to discharge capacitor C_(sample). After this discharge, resettransistor M1 is switched off, and the charge is transferred to thefloating diffusion FD by pulsing the transfer gate TG. This signal isthen sampled on C_(sample). After the sampling process, M3 is switchedoff again. An advantage of this schematic is the lack of a ground linein the pixel, and the pixel requires one less transistor (a total of sixtransistors).

FIG. 4 c shows another embodiment of the pixel. In this embodiment, theselect transistor (M5 in previous drawings) is eliminated as well. Theoutput (source) of buffer amplifier M4 is connected directly to thecolumn output line 15. The input (gate) of buffer amplifier M4 isconnected to the output (source) of buffer amplifier M2. The sampletransistor M3 and the sample capacitor C_(sample) are connected inseries between the gate of M4 and a fixed bias level (ground, VDD oranother fixed voltage). In this way, the signal held on the samplecapacitor C_(sample) is shielded by the sample transistor M3. The gateof M4 is kept at a low level for most of the time through transistor M2.During the sampling process, transistor M3 is pulsed to store the signalon C_(sample).

For most of the time, the voltage on the DISCHARGE line is low (groundor a low voltage) whilst RESET is kept high. This keeps the source of M2at a low voltage (the voltage applied to the DISCHARGE line, normallyground). The capacitor C_(sample) is discharged by pulsing the SAMPLEline high for some time, so that transistor M3 is conductive and samplesthis low voltage.

For readout of the photodiodes, the RESET line is set low to put thesense node FD at a floating potential, and the DISCHARGE signal line isset to a high voltage. Then the transfer gate is pulsed. The voltage onthe floating diffusion FD will fall, and so will the voltage at thesource of M2. M3 is conductive at this moment and will sample thevoltage at the source of M2. Then the SAMPLE line goes low again to openswitch M3, and a next exposure can start on the photodiode 11. Duringreadout, the lines are scanned row-by-row. For all rows except the rowthat is read out, the DISCHARGE line is kept low (near ground) and theRESET line is kept high. This keeps the gate of M4 at ground potential,and the pixels do not control the column output line. For the row whichis read out, the DISCHARGE line is raised to a high voltage. This putsthe reset level at the gate of M4, and this signal is transferredthrough source follower M4 to the column line. To read out the valuesampled on C_(sample), the floating diffusion FD is pulled to a lowvoltage by putting a low voltage on the READ line for the row that isread out. This switches off M2. Then transistor M3 is closed by pulsingSAMPLE for the row that is read out, and the voltage swing is measuredat the output of the pixel on the column line. It is also possible touse the VDD line to control read out, using a more complex timingarrangement.

FIG. 4 d shows an alternative embodiment to that of FIG. 4 b, in whichthe drain of reset transistor M1 is also tied to the discharge line. Thetiming of the discharge line is adapted to ensure that the floatingdiffusion is at a high voltage at the moment when the capacitorC_(sample) needs to be discharged. To discharge, the DISCHARGE controlline is pulsed to a low voltage and M3 is conductive at that moment.This embodiment may result in more efficient routing inside the pixel,depending on the exact pixel layout. A possible disadvantage is that thefloating diffusion FD is also pulsed.

FIG. 5 shows another embodiment of the pixel. The numbering conventionof the transistors is different to previous embodiments. In thisembodiment, two photodiodes pd1, pd2 are coupled to a partially commonpixel readout circuit. The first photodiode pd1 is connected via adedicated transfer gate 1 to the floating diffusion FD. The secondphotodiode pd2 is also connected via a dedicated transfer gate 2 to thefloating diffusion FD. There is a single reset transistor M1 and asingle first buffer amplifier M2, which are shared by both photodiodes.There is also a single second buffer amplifier M7 and a single readtransistor M8 which are shared by both photodiodes. There are individualsample and storage stages for each of the photodiodes: a first of thesecomprises transistors M3, M5 and sample capacitor C1; the secondcomprises transistors M4, M6 and sample capacitor C2. There is a singledischarge transistor M9 for discharging sample capacitors C1, C2. In thesampling process, first the signal of photodiode 1 is transferred to thefloating diffusion FD and copied to storage capacitor C1. The floatingdiffusion FD is reset and then the signal of photodiode 2 is transferredto the floating diffusion FD and copied to storage capacitor C2. Thesignal stored on each of the storage capacitors C1, C2 is read outthrough source follower M7, and switches M5, M6 and M8. The signals onC1, C2 are read one at a time. Transistor M9 acts together with eitherM5 or M6 to discharge the capacitors C1 or C2 before the floatingdiffusion FD signal is sampled. The arrangement shown in FIG. 5 can beextended to other numbers of photodiodes, with each additionalphotodiode requiring a transfer gate and a sample and storage stage(transistors M3, M5 and capacitor C1) but sharing other components. Thenumber of photodiodes will typically be limited by layout constraints.Another advantageous configuration (not shown) is a shared readout for agroup of four photodiodes arranged in a 2×2 array. The readout sectioncan be located in the centre of the four photodiodes. An advantage ofthese configurations with a (partially) shared readout structure is amore compact layout.

FIG. 6 shows a readout architecture for double sampling in the columnand output amplifiers. The overall image sensor comprises an array ofthe pixels described in any one of FIGS. 2-5. Typically, the individualpixels are arranged in rows and columns, with control lines extendingparallel to the rows and/or columns and output lines per column ofpixels. FIG. 6 shows one pixel 10 (the pixel of FIG. 2) which can beselectively connected to a column output line via a READ switch. A largenumber of similar pixels will also be selectively connected to the samecolumn output line in a time-multiplexed manner. Each column has acolumn output stage 50 which comprises a column amplifier and associatedhardware. An output stage receives inputs, in a time-multiplexed manner,from the column output stages. In use, each pixel in a column of pixelsis read, in a time-multiplexed manner, by connecting the pixel to thecolumn output line via the READ switch. A row of pixels can besimultaneously read in this way, with each pixel in the row outputting asignal to a respective column output line. Outputs from the set ofcolumn amplifiers are applied, in a time-multiplexed manner, to theoutput stage.

The output amplifier 60 calculates the difference between the twosamples (reset level, signal value) obtained from each pixel. Thesubtraction works as follows. For each pixel, the reset and signalvalues are passed sequentially to the input of the output amplifier viathe multiplexer bus. When the first sample (e.g. reset value) is appliedto the input of the output amplifier 60, the switch ‘Clamp’ is closed.The first sample is then sampled on the series capacitor C_(clamp).Then, the switch opens again and the second sample (e.g. signal value)is applied to the input of the amplifier (at the left side of the seriescapacitor). At the other side of the series capacitor C_(clamp) thedifference between the second sample and first sample will appear. Theclocking of the ‘clamp’ switch is illustrated in the timing diagram ofFIG. 9. The second switch and capacitor in the amplifier are used as atrack and hold. This stage will track the signal (switch closed) whenthe subtracted signal is available at the output of the first buffer(this is when the second sample is applied), and will be in hold (switchopen) when the first sample is applied (the differential signal of theprevious sample is then still available at the output of the outputamplifier). There are various known alternative schemes for processingthe outputs of a pixel array which can be used in place of the onedescribed here. For example, a column processing unit associated witheach column of the pixel array can perform an analog-to-digitalconversion of the difference between the reset level and the samplesignal.

FIGS. 7 a and 7 b show timing diagrams for the acquisition of an imageand storage of the image in the pixel sample capacitors C_(sample). FIG.7 a shows the timing for a pixel as in FIG. 4 a, with a dedicateddischarge transistor M6. FIG. 7 b shows the timing for a pixel as inFIG. 4 b or 4 c in which the capacitor C_(sample) is discharged via thesource follower M2.

Referring to FIG. 7 a, the exposure time for the photodiode 11 starts assoon as the transfer gate TG is opened. Towards the end of the exposureperiod, the floating diffusion is reset, and the reset switch opensagain (t1), in preparation for the transfer of charge from thephotodiode 11. The sample capacitor C_(sample) is also discharged inpreparation for sampling the signal of the photodiode. At t2, towardsthe end of the exposure period, the transfer gate TG is pulsed for allpixels of the array in parallel (global shutter). Charge is transferredfrom the pinned photodiode 11 to the floating diffusion FD of the pixel.The exposure period ends when the transfer gate TG is opened at t3. Att4 the signal is sampled by pulsing the sample transistor M3.Optionally, the reset switch M1 and transfer gate TG close again toreset the floating diffusion FD and evacuate any remaining charge on thephotodiode 11. The next exposure time starts at t5 as soon as thetransfer gate is released. The state of the reset line during theexposure can be low but is advantageously kept high. When kept at a highlevel, it keeps the floating diffusion FD at a high voltage at alltimes. Excess charge on the photodiode in case of overexposure of thepixel can be drained away via the transfer gate and reset transistor inthis case. The sampled signal level, which is now stored on the samplecapacitor C_(sample), can be read at any point during the next exposureperiod. After readout of the value on C_(sample), the reset level isread out to provide a reference offset level of the pixel. To do that,the SAMPLE line is pulsed for the row that is read out. This brings thereset level to the gate of M4. This operation is typically performedafter readout of C_(sample). In FIG. 7 b the DISCHARGE line is set lowat the moment when the sample capacitor C_(sample) needs to be reset.The floating diffusion FD is at a high voltage at this moment and thisensures that M2 is conductive.

FIG. 8 shows a timing diagram for a double sampling operation using thearchitecture of FIGS. 6 and 7 during readout of the signals stored onthe pixel sample capacitors C_(sample). The double sampling operationfor readout is as follows:

-   -   1. A row of pixels is selected, at t1, by activating the read        transistor in the pixels of that row. The signals of the row of        pixels appear on the respective column output lines.    -   2. At t2, the signal of the column line is sampled in column        capacitor Cs by closing switches S and SS(x) in each column.        Meanwhile, the floating diffusion FD is reset (or kept in the        reset state) by closing the reset transistor M1 in the pixel.    -   3. At t3, the sample switch M3 in each of the selected row of        pixels is closed. The capacitor C_(sample) in the pixel samples        the reset level. This reset level is buffered by the second        buffer amplifier AMP2 in the pixel and appears at the pixel        column output line.    -   4. At t4, the signal of the column output line is sampled on        column capacitor C_(R) by closing switches S and SR(x) in each        column.    -   5. At t5 the readout of the signals stored in the column        amplifiers starts, by scanning sequentially through the columns,        and multiplexing signals from capacitors Cr(x) and Cs(x) of each        column on the multiplexer bus for each column (x).    -   6. The output amplifier calculates the difference between the        signals of Cr(x) and Cs(x) for each column (x).

The pixel can also be operated with correlated double sampling (CDS),via another timing scheme:

-   -   1. The floating diffusion is reset.    -   2. The reset level is sampled on sample capacitor C_(sample)        through the first buffer amplifier AMP1 and the sample switch        M3;    -   3. The signal of the photodiode 11 is transferred to the        floating diffusion FD through transfer gate TG. This ends the        exposure time, and starts a new exposure time. The signal        remains stored on the floating diffusion FD during the readout.    -   4. The array is read out. Firstly the reset level stored on the        sample capacitor is read out, and then secondly the signal of        the floating diffusion FD is sampled on the sample capacitor and        read out.        This mode does not allow to reduce the exposure time below the        frame readout time. The read noise of the pixel is lower. The        kTC noise on the floating diffusion is correlated on the reset        and signal samples, and hence cancelled by the correlated double        sampling operation in the column and output amplifiers. The        drawbacks of this method are an increased parasitic light        sensitivity of the storage node (floating diffusion) and leakage        current on the floating diffusion storage node that may disturb        the stored signal. These disadvantages are not so important at        very high frame rates since the time of storage of the signal on        the floating diffusion is short.

In each of the embodiments described above, the photodiode is preferablya pinned photodiode as this gives the best performance, but theinvention is not limited to pinned photodiode pixels only. Lessadvantageously, it is possible to use a non-pinned photodiode. Thiswould allow fixed pattern noise correction combined with a pipelinedsnapshot shutter, and keeps the parasitic light sensitivity low.However, the charge on the photodiode will be divided between thephotodiode and the floating diffusion, rather than being (fully)transferred. If the capacitance of the photodiode and floating diffusionare equal, only half of the charge will appear on the floatingdiffusion. So the signal will have only half the amplitude, or thesignal-to-noise ratio will be half as good.

For a triggered global shutter mode of operation, it is possible to usethe timing schemes described in FIGS. 7 a and 7 b but with readoutbefore the next exposure period starts.

Advantageously, low threshold voltage transistors are offered in CMOStechnologies for certain functions. If this is the case, a low-voltagetransistor can be utilized for reset transistor M1, and source followersM2 and M4 in the pixel of FIG. 4 a. With the given timing and biaslevels of these transistors, the higher leakage of low-voltagetransistors does not influence the performance of circuit. In contrast,the pixel disclosed in U.S. Pat. No. 6,847,070 cannot allow a lowthreshold voltage device for the reset transistor M1 because of theincreased leakage current of low voltage transistors. Since the signalis stored on the floating diffusion in that pixel, which is connected tothe source of M1, the leakage current of M1 will disturb the signalsample during storage on the floating diffusion in that pixel. A similardisadvantage exists for U.S. Pat. No. 7,224,389 in which the resettransistor is directly connected to the photodiode and in which leakageon the reset transistor will disturb the signal acquired on thisphotodiode.

Other timing schemes may also be applied. In the above description, thefeedthrough signal of the reset line RESET from the gate of the resettransistor M1 onto the floating diffusion FD is not cancelled in thedouble sampling process, because the reset line is assumed to be highall the time during readout. This feedthrough can be cancelled, ifrequired, by pulsing the reset line RESET for the row as it is read out.The reset line RESET is pulled low before sampling the reset level onthe sample capacitor in the double sampling operation. This is not shownin the timing diagram of FIG. 8. Also, it may be advantageous to performan extra discharge of the sample capacitor C_(sample) in the pixelduring readout, before sampling the reset level. This is also not shownin FIG. 9.

The pixels described above have a storage capacitor C_(sample). In mostembodiments, this is used to store a sample of the signal level (i.e.the exposure level of the photodiode) until it can be read by thereadout circuitry. This allows pipelined global shutter operation, asthe signal level can be stored while the photodiode is exposed toradiation. Double sampling is possible, by reading the signal level heldon the storage capacitor followed by reading the reset level of thesense node. The pixel has a noise determined by the kTC noise of thefloating diffusion. The temporal noise level is 21 electrons withoutfixed pattern noise (FPN) correction, and increases to 30 electronsafter FPN correction through double sampling (with a 3.7 fF floatingdiffusion capacitor). This increase is caused by the fact that the kTCnoise is uncorrelated on both samples operated during the doublesampling process. The fixed pattern noise on an uncorrelated pixel canbe up to 100 mV peak-to-peak. With double sampling this is reduced to 1mV peak-to-peak, or less. Correlated double sampling (CDS) is alsopossible with the pixel described above by storing the reset level onthe storage capacitor and storing the signal level on the sense node.The photodiode can capture the next frame while the reset and signallevels of the previous frame are read out. The only constraint is thatthe exposure time has to end after the readout of pixel array as theexposure time ends only when the charges are moved from the diode to thefloating diffusion.

FIGS. 9 to 12 show further embodiments of the pixel in which a secondstorage stage 30 is added to the pixel. In FIGS. 9 and 10 the secondstorage stage is arranged in parallel with the first storage stage. InFIGS. 11 and 12 the second storage stage is arranged in cascade with thefirst storage stage. In FIG. 9 the first storage stage is shown as item20, and the capacitor is now called C_(signal). Each storage stage 20,30 is connected to an output of the first buffer amplifier AMP1. Eachstorage stage 20, 30 has a sample switch/transistor SAMPLE, a storagecapacitor C_(signal), C_(reset), and an output buffer amplifier AMP2,AMP3. In this embodiment, each storage stage 20, 30 connects to adedicated output line 15, 16.

The pixel shown in FIG. 9 can be operated as follows:

-   -   1) Charge is integrated on the pinned photodiode during the        exposure time.    -   2) The floating diffusion is reset. The reset level is sampled        on capacitor C_(reset).    -   3) Charge is transferred from the photodiode to the floating        diffusion. The signal level at the floating diffusion is        sampled, and stored, on capacitor C_(signal). This ends the        exposure time.    -   4) The image is read out by reading the values stored in the        pixel capacitors C_(reset) and C_(signal). During readout, the        difference between the two signals is calculated. This cancels        any kTC noise on the floating diffusion, and it is thus a true        correlated double sampling readout. During this readout, the        photodiode can be exposed to radiation for the next frame.        This pixel can also support other operational modes:    -   1. true differential imaging. Two images are acquired shortly        after one another. This can be used to analyze very fast events,        or for tracking moving objects. A signal value for a first frame        is stored in one of the storage stages 20, 30. A signal value        for a second frame is stored in the other of the storage stages        20, 30. The difference between the stored signal values of the        two frames can be calculated on chip, by processing circuitry        located in the column output stages of the array, or by        additional circuitry within each pixel.    -   2. acquisition of two images with different exposure times, for        increased dynamic range. This gives an alternative to multiple        slope integration. Operation is as described above, with the        added feature that the exposure period of the photodiode is        varied between the first frame and the second frame.

Another advantage of this embodiment of the pixel is that the resetlevel is sampled just before the charge transfer from the photodiode tothe floating diffusion. This is at the end of the exposure time. Thismeans that the reset sample stored on the reset capacitor C_(reset) isnot influenced by parasitic light during the exposure time. Parasiticlight sensitivity is the same for the reset and signal samples, andhence it will be extremely small after the CDS operation. The remainingnoise in such differential pixels is the source follower noise, which ismainly a 1/f noise component. Since the time interval between the resetand signal samples is very low in the pinned diode differential pixel,the 1/f noise contribution is small. The low-frequency part of the 1/fnoise appears as correlated noise. The remaining dominant noise in thispixel is kTC noise on the sample capacitors, which is uncorrelated. Thepixel will also feature a much lower fixed pattern noise.

In FIG. 9, each of the two storage stages 20, 30 has an output bufferamplifier AMP2, AMP3. Both stored signals are read out at the samemoment in time, simplifying the column differential amplifier andspeeding up pixel access. This is a particularly advantageousarchitecture to obtain a low noise, high-speed, readout.

FIG. 10 shows an alternative form of the pixel in which the two storagestages 20, 30 are read out serially through the same buffer amplifier.Each stage 20, 30 has a switch READ_S, READ_R which can be selectivelyclosed to connect the capacitor in one of the stages 20, 30 to theoutput buffer amplifier AMP2. This pixel will cancel the offsetvariations of all transistors in the pixel. This will increase the pixelaccess time, as a single output line must be used to read both storedvalues.

Alternatively, the offset variations of amplifiers AMP2 and AMP3 in FIG.9 can be corrected by reading an extra reference level after dischargingC_(sample) and C_(reset), or after bringing the inputs of AMP2 and AMP3to the same reference level. This reading can occur immediately afterthe reading of the sampled values on capacitors C_(sample) andC_(reset).

The pixels shown in FIGS. 9 and 10 require additional circuitry perpixel, which will lower the fill factor. However, the difference in fillfactor may be entirely compensated by the lower noise of the pixel.

The embodiments shown in FIGS. 9 and 10 retain the other advantagesdescribed above, such as anti-blooming protection through the transfergate and reset transistor, without requiring additional anti-bloomingcircuitry.

The embodiments shown in FIGS. 9 and 10 can be applied to shared pixels,where two photodiodes share one pair of storage stages 20, 30. Signalsfrom only one of the two photodiodes can be stored in the storage stages20, 30 to give a sub-sampled image. Alternatively, the signals of thetwo photodiodes can be added together on the sense node, by operatingboth transfer gates with the same timing signals, to give a ‘binned’image that can be stored with CDS in the 2 memory elements. A furtheralternative is to store the images of the two different photodiodes inthe two storage stages and subtract them on-chip to obtain a kind of‘sobel’ filtered image. Only the edges will be visible in that image.

FIGS. 11 and 12 show a pixel with two storage stages 120, 130 arrangedin cascade. This has an advantage over the parallel arrangement ofsample stages 20, 30 in FIGS. 9 and 10 of requiring fewer components.Also, the parasitic capacitance at the readout node can be problematicin the case where the sample capacitors cannot be made relatively large.These disadvantages are addressed by this cascade arrangement.

The pixel is operated as follows (see FIGS. 13 a and 13 b). At the endof the integration period, the sense node FD is reset and the value ofthe sense node FD (the reset value of the pixel) is sampled on capacitorC1 (through sample 1 and sample 2 switches). In this phase, whensampling the reset value of the FD, both C2 and C1 are charged. This isnot a problem, because this happens after readout of all the signals inthe array (i.e. during “frame blanking time”). Charges are transferredfrom the photodiode into the sense node FD by pulsing the transfer lineTx. The signal value is then sampled on capacitor C2 by operating thesample 2 switch. During readout (see FIG. 14), the pixel is selected andthe reset signal on capacitor C1 is first readout (phase 1). The sample1switch is then closed and there will be charge sharing between C1 and C2(phase 2). The sample1 switch is then again opened (phase 3). Neglectingany attenuation from the source followers, voltage threshold shifts andclock feedthrough, the signal that is readout during phase 1 is:

V _(output) =V _(reset) +v _(noise,fd) +v _(noise,C1)  (1)

where V_(reset) is the reset value of the pixel and v_(noise,fd) andv_(noise,C1) are the kTC noise contributions from C_(FD) and C₁respectively.During phase 2, when the sample 1 switch is closed, the output voltageis:

V _(output) =V _(reset) +v _(noise,fd)+(C ₁/(C ₁ +C ₂))×v _(noise,C1)+(C₂/(C ₁ +C ₂))×v _(noise,C2)−(C ₂/(C ₁ +C ₂))×V _(signal)  (2)

with V_(signal) the light induced voltage drop of the pixel andv_(noise,C2) the kTC noise contribution from C₂.During the phase 3 a non-correlated kTC noise contribution v*_(noise,C1)is added:

V _(output) =V _(reset) +v _(noise,fd)+(C ₁/(C ₁ +C ₂))×v _(noise,C1)+(C₂/(C ₁ +C ₂))×v _(noise,C2)−(C ₂/(C ₁ +C ₂))×V _(signal) +v*_(noise,C1)  (3)

Subtracting (3) from (1) yields

V _(signal)=(C ₂/(C ₁ +C ₂))×V _(signal)+(C ₂/(C ₁ +C ₂))×(v _(noise,C1)+v _(noise,C2))+v* _(noise,C1)

Note that the output signal of phase 2 can also be used, but it mayexhibit a pixel variant offset from clock feedthrough of sample1. Thepixel fixed pattern noise may therefore not be cancelled completely butthe temporal read noise will be lower.

The main advantage of this pixel architecture with cascaded samplingcompared to single sampling architectures is that it allows truecorrelated double sampling of the FD in pipelined synchronous shutteroperation. It will therefore result in considerably better noiseperformance. Also, since the shutter efficiency for both samples can bemade to be virtually equal, the remaining parasitic light sensitivitywill be very small.

FIG. 11 shows a precharge transistor PC connected between the source ofthe buffer amplifier M2 and ground. The function of transistor PC is todischarge the capacitor C2 before it is recharged by the source followerto its final value. At the moment the reset level is sampled on C1, italso discharges C1 through the two sample switches. It also acts as acurrent source for the buffer amplifier M2.

In FIG. 12, the precharge transistor of FIG. 11 is omitted and the drainof transistor M2 is connected to a discharge line instead. Transistor M2now acts both as precharge transistor (when discharge line is pulledlow) and as source follower (when discharge line is pulled high). FIGS.13 a and 13 b show timing diagrams for the acquisition of an image andstorage of the image in the two pixel sample capacitors C1 and C₂. FIG.13 a shows the timing for a pixel as in FIG. 11, with a dedicatedprecharge transistor M6. The PC bias line can be kept continuously highas well, operating the transistor M6 as current source for the sourcefollower. FIG. 13 b shows the timing for a pixel as in FIG. 12 in whichthe capacitors are discharged via the source follower M2.

The various forms of pixel described above can be used to effect aglobal shutter (pipelined mode or triggered mode) with double sampling,or correlated double sampling. The storage capacitor C_(signal), storagecapacitor C_(reset), sense node and photodiode can all serve as memoryelements. For a basic pipelined shutter, with no double sampling/CDS,two memory elements are required: one memory element to store the signalvalue of the previous image and one to store the image that is acquired.For a pipelined shutter with double sampling three memory elements arerequired: one to store a signal value of the previous image; one togenerate/store a reference level during readout without disturbing thephotodiode (with uncorrelated noise); and one for the image beingacquired. A pipelined shutter with correlated double sampling is alsopossible with three memory elements, if the signal level is stored onthe sense node (not ideal). For a pipelined shutter with correlateddouble sampling, four memory elements are ideally required: a memoryelement to store the reference (reset) level of the previous image (withcorrelated noise); a memory element to store the signal of the previousimage and a photodiode to store the image being acquired. The sense nodealso serves as a kind of a memory element to provide a reference beforereadout of the diode without destroying the photodiode signal. Theadvantage compared with the case where a pipelined shutter withcorrelated double sampling is implemented using only three memoryelements, there is no need to store a photodiode signal on the sensenode, which is not an ideal storage element.

Various methods of operating the pixels and/or pixel arrays arepossible. These are set out below.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a sample stage connected toan output of the first buffer amplifier and a second buffer amplifierhaving an input connected to the sample stage, the method comprising:generating charges at a photo-sensitive element in response to incidentradiation; resetting the sense node; operating the transfer gate totransfer charge from the photo-sensitive element to the sense node;causing the sample stage to sample a signal on the sense node whichrepresents an exposure level of the pixel; reading the sampled exposurelevel of the pixel; resetting the sense node; causing the sample stageto sample a signal on the sense node which represents a reset level ofthe pixel; and, reading the sampled reset level of the pixel.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a sample stage connected toan output of the first buffer amplifier and a second buffer amplifierhaving an input connected to the sample stage, the method comprising:generating charges at a photo-sensitive element in response to incidentradiation; resetting the sense node; causing the sample stage to samplea signal on the sense node which represents a reset level of the pixel;operating the transfer gate to transfer charge from the photo-sensitiveelement to the sense node; reading the sampled reset level of the pixel;causing the sample stage to sample a signal on the sense node whichrepresents an exposure level of the pixel; and, reading the sampledexposure level of the pixel.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a first sample stageconnected to an output of the first buffer amplifier and a second samplestage connected to an output of the first buffer amplifier, the methodcomprising: generating charges at a photo-sensitive element in responseto incident radiation; resetting the sense node; causing the firstsample stage to sample a signal on the sense node which represents areset level of the pixel; operating the transfer gate to transfer chargefrom the photo-sensitive element to the sense node; causing the secondsample stage to sample a signal on the sense node which represents anexposure level of the pixel; and, reading the sampled exposure level ofthe pixel and the sampled reset level of the pixel.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a first sample stageconnected to an output of the first buffer amplifier and a second samplestage connected to an output of the first buffer amplifier, the methodcomprising: generating charges at a photo-sensitive element in responseto incident radiation; resetting the sense node; operating the transfergate to transfer charge from the photo-sensitive element to the sensenode; causing the first sample stage to sample a signal on the sensenode which represents a first exposure level of the pixel; generatingcharges at a photo-sensitive element in response to incident radiation;resetting the sense node; operating the transfer gate to transfer chargefrom the photo-sensitive element to the sense node; causing the secondsample stage to sample a signal on the sense node which represents asecond exposure level of the pixel; and, reading the sampled exposurelevels of the pixel.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a first sample stageconnected to an output of the first buffer amplifier and a second samplestage connected in cascade with the first sample stage, the methodcomprising: generating charges at a photo-sensitive element in responseto incident radiation; resetting the sense node; causing the secondsample stage to sample a signal on the sense node which represents areset level of the pixel; operating the transfer gate to transfer chargefrom the photo-sensitive element to the sense node; causing the firstsample stage to sample a signal on the sense node which represents anexposure level of the pixel; and, reading the sampled reset level of thepixel and then the sampled exposure level of the pixel.

A method of operating a pixel, the pixel comprising a photo-sensitiveelement, a sense node and a transfer gate connected between thephoto-sensitive element and the sense node, a first buffer amplifierhaving an input connected to the sense node, a first sample stageconnected to an output of the first buffer amplifier and a second samplestage connected in cascade with the first sample stage, the methodcomprising: generating charges at a photo-sensitive element in responseto incident radiation; resetting the sense node; operating the transfergate to transfer charge from the photo-sensitive element to the sensenode; causing the second sample stage to sample a signal on the sensenode which represents a first exposure level of the pixel; generatingcharges at a photo-sensitive element in response to incident radiation;resetting the sense node; operating the transfer gate to transfer chargefrom the photo-sensitive element to the sense node; causing the firstsample stage to sample a signal on the sense node which represents asecond exposure level of the pixel; and, reading the sampled firstexposure level of the pixel and then the sampled second exposure levelof the pixel.

FIG. 15 shows an overall architecture for a pixel array/image sensor. Asimplified four pixel by four pixel array is shown. Each pixel 10 is aspreviously shown in FIGS. 2, 3, 4 a-4 d, or a set of pixels with ashared read out circuitry as shown in FIG. 5. A controller 135 includesrow selection/line driver circuitry 130 for driving pixels in the array.Controller 135 controls selection of pixels, and generates the controlsignals RESET, TRANSFER, SAMPLE, DISCHARGE and SELECT to control eachpixel. The timing of these control signals will be described below withreference to FIGS. 7 a, 7 b and 8. Controller 135 can perform a globalshutter function by synchronising operation of the control signals whichcontrol respective exposure times of each of the pixels of the array.Controller 135 also controls, via column processing circuitry 138,operation of the column amplifiers and read out from the columnamplifiers. The control logic of controller 135 can be stored inhard-coded form, such as in an Application Specific Integrated Circuit,or it can be stored in some form of reconfigurable storage, such as alogic array (programmable array, reconfigurable array) or ageneral-purpose processor which executes control software. All of theelements shown in FIG. 15 can be provided on a single semiconductordevice or the elements can be distributed among several separatedevices.

The invention is not limited to the embodiments described herein, whichmay be modified or varied without departing from the scope of theinvention.

1. A pixel comprising: a pinned photodiode for generating charges inresponse to incident radiation; a sense node; a transfer gate, connectedbetween the pinned photodiode and the sense node, for controllingtransfer of charges to the sense node; a reset switch connected to thesense node for resetting the sense node to a predetermined voltage; afirst buffer amplifier having an input connected to the sense node; asample stage, connected to an output of the first buffer amplifier,which is operable to sample a value of the sense node; and, a secondbuffer amplifier having an input connected to the sample stage.
 2. Apixel according to claim 1 wherein the sample stage comprises: a sampleswitch connected to an output of the first buffer amplifier; and, astorage element for storing a signal level sampled by the sample switch.3. A pixel according to claim 1 further comprising a discharge switchfor resetting the sample stage.
 4. A pixel according to claim 1 whereinthe first buffer amplifier is connected to a first control line which isoperable to discharge the sample stage.
 5. A pixel according to claim 4wherein the reset switch is also connected to the first control line. 6.A pixel according to claim 1 further comprising a read switch connectedto the output of the second buffer amplifier for reading a signal fromthe pixel.
 7. A pixel according to claim 4 wherein the sample stagecomprises a sample switch connected to a first node and a storageelement connected in series with the sample switch and wherein both ofthe input to the second buffer amplifier and the output of the firstbuffer amplifier are connected to the first node.
 8. A pixel accordingto claim 1 and control circuitry which is arranged to: operate the resetswitch to reset the sense node; operate the transfer gate of the pixelto transfer charge from the pinned photodiode to the sense nodefollowing exposure to radiation; cause the sample stage of the pixel tosample the signal on the sense node, which sampled signal represents anexposure level of the pixel.
 9. A pixel according to claim 8 wherein thecontrol circuitry is further arranged to: read the sampled exposurelevel of the pixel; and subsequently, to: cause the sample stage tosample the sense node after it has been reset, which sampled signalrepresents a reset level of the pixel; and, read the sampled reset levelof the pixel.
 10. A pixel according to claim 8 wherein the controlcircuitry is arranged to operate the reset switch of the pixel while thepinned photodiode of the pixel is being exposed to radiation.
 11. Apixel according to claim 10 wherein the control circuitry is arranged tooperate the reset switch at all times other than when it is required totransfer charge to the sense node and sample a value of the sense node.12. A pixel according to claim 1 and control circuitry which is arrangedto: reset the sense node; cause the sample stage to sample a signal onthe sense node which represents a reset level of the pixel; operate thetransfer gate to transfer charge from the pinned photodiode to the sensenode following exposure to radiation, which transferred chargerepresents an exposure level of the pixel; read the sampled reset levelof the pixel; cause the sample stage to sample a signal on the sensenode which represents an exposure level of the pixel; and, read thesampled exposure level of the pixel.
 13. A pixel array comprising anarray of pixels according to claim
 1. 14. A pixel array according toclaim 19 and control circuitry which is arranged to cause the array ofpixels to be exposed synchronously.
 15. A pixel array according to claim19 and wherein the control circuitry is arranged to read a value storedin the sample stage of a pixel in the array for a first exposure periodwhile the pinned photodiode of the pixel is exposed for a secondexposure period.
 16. A pixel comprising a photo-sensitive element forgenerating charges in response to incident radiation; a sense node; atransfer gate, connected between the photo-sensitive element and thesense node, for controlling transfer of charges to the sense node; areset switch connected to the sense node for resetting the sense node toa predetermined voltage; a first buffer amplifier having an inputconnected to the sense node; a first sample stage, connected to anoutput of the first buffer amplifier, which is operable to sample areset level of the sense node; a second sample stage connected to anoutput of the first buffer amplifier which is operable to sample a valueof the sense node; a second buffer amplifier having an input connectedto an output of the first or second sample stages.